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LDmicro Forum - Theoretical interpreter resource requirements? |
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Theoretical interpreter resource requirements? (by Mike Panetta)
I have not downloaded anything yet, so this question may be a bit premature, but do you have any idea what the resource requirements of the interpreter would be?
I am wondering because it may be ideal to load the bit/bytecode into a serial eeprom/fram and run it directly from there, in a chip such as a Cortex-M3. ST Micro has a really small one that is in a 48QFP that would be perfect for a small PLC.
(no subject) (by Jonathan Westhues)
That Cortex part should be more than capable. The overhead for interpreted vs. compiled code is probably not more than 5 (assuming that you load the serial EEPROM into memory-mapped memory at startup), and the Cortex has ~5x as many MIPS as a typical AVR. So interpreted code on the Cortex is probably about as fast as compiled code on the AVR.
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