|
LDmicro Forum - Porting LDMicro to Cortex-M0 |
|||
|
|
|
(you are viewing a thread; or go back to list of threads)
Porting LDMicro to Cortex-M0 (by Xavier)
Hi
First of all let me say that I admire you because of your hard work for making this useful application. I want to ask if you have a kind of internals' documentation so I can start porting it to the Cortex-M0 or Cortex-M3 microcontrollers. Otherwise, would you point me out to the code's section I need to look at first? Other question: how, o where in the code, inputs/outputs are mapped to GPIOs or RAM? Another question: The application has the option to choose "byte -code" output, how this byte-code is formatted? Thank you!! And I hope to start porting LDMicro soon.
(no subject) (by Jonathan Westhues)
It wouldn't be possible to write a general back end targeting any Cortex-M0 or -M3 processor; since LDmicro generates not just code for the user's program but also the runtime and peripheral interface firmware (to run the program at the specified cycle period, or drive GPIO pins, or run the A/D, or ...), the code depends not just on the processor instruction set but also on its memory-mapped peripherals. In an ARM microprocessor, those peripherals are generally designed by the silicon vendor, not ARM, and vary from vendor to vendor.
You could do that for a particular series of ARM microcontrollers, though; or you could write a bytecode interpreter instead, since an ARM microcontroller will generally have more than enough memory and execution speed for that. See ldinterpret.c, for example, for some documentation of that file format. Oh, and for the mapping: the user interface with which the user can specify the mapping from physical I/O pins to relays, coils, A/D instructions, etc. is in iolist.cpp. The mapping of that assignment to physical addresses, and the assignment of general-purpose RAM to internal variables, is in compilecommon.cpp, in the MemFor... functions.
(no subject) (by Xavier)
Hi
Thank you for the highlights. Porting it to every ARM Cortex processor would be impossible, as you said, that's way I thought in a layered architecture: -------------------------------+ PLC layer | -------------------------------+ Device Drivers Layer | FreeRTOS| -------------------------------+ HAL layer | -------------------------------+ Hardware | -------------------------------+ This way I can bypass any vendor particularity, and in most chips memory isn't really an issue. In the other side, I also thought about a virtual machine, or byte-code interpreter. But it's also possible that the compiler emits native Cortex code. I have loocked over the code, but I think that, in order to make the code more portable, I can add a Config.h file. In this file would be the GPIO mapping and other stuff. As soon as I get some free time, I'll start the porting. Hope you don't mind if I keep making you technical questions. Kind regards :)
PLC ladder (by Hassan)
Hi Xavier,
Did you do this project and port this program for ARM Cortex M3? I'm searching about design a PLC with ARM with ladder compiler. Who can introduce me about design a PLC with ARM? Regards
Re ARM and ladder (by Dave)
Maybe you can use Energia IDE and follow the same instructions for using ldmicro generated code to program an arduino. I use a Launchpad Tiva C and energia, It should be straight forward.
Post a reply to this comment:
|
|
|