I propose to implement one fixed memory allocation and to map
this to different cpu´s. PWM are mapped to OR, ADC to IR.
For UART TX should use read only memory and steps in order to
sequenziate the string output using the SF memory for putting
out chars to the serial line.

My suggested memory allocation is this:
=bit registers
X(256) input, map to external inputs
Y(256) output, map to external output
T(256) timer
C(256) counter
TR(40) temporary
S(1000) steps
M(2002) marker
=file registers (16bit)
SR(328) special registers
HR(200) hardware register
T(256) timer
C(256) counter , 200 16bit, 56 32bit
IR(64) map to external AD
OR(64) map to external DA
R(3840) Register (can be configured to retentive)
D(3072) Register non retentive
-----------------------------
ROR(3072) read only register

As example, if using 14pin PIC having porta A+C and the
pic has 4 output relais and 8 inputs,
X0-5 and x24-25 is valid as input (A0-6 and C0-1)
and Y26-29 is the output (C2-C5)

At the same time, if using 18pin Pic devices with the
same configuration and i2c expansion bus and using 16bit
i2c expansions with 8 possible addresses the i2c expansion
can be mapped to X/Y128-255

Indipendently of input/output (X/Y) the address space is one,
X123 is for reading and Y123 for writing, but the hw bit is one. However there are hw mask (Xor+And) indipendently for input and output that specify what bits are input and output and if there should be inverted or not.

There should be a tool that allows remapping of pins
from one cpu to annother.

What do you think ?